1. Field of the Invention
The invention relates to a process for the fabrication of submicron copper interconnection on integrated circuit structure by depositing directly a metal layer on the resist layer via displacement deposition to replace the original copper seed layer, followed by copper electroplating to form a submicron copper interconnection.
2. Description of the Related Prior Art
In order to coordinate the increasingly smaller but higher efficient integrated circuit (IC), the fabrication of the interconnection must meet the requirement of deep submicron level. However, due to properties such as resistance, electromigration impedance and the like, aluminum used in traditional process becomes no more advantageous. On the contrary, copper exhibits several advantages such as low resistance, higher melting point, as well as better electromigration impedance. Further, problems associated with the prior art, such as the unavailability of reactive ion etching process and the diffusion into oxide layer, have now been overcome through the research and development of Dual Damascene process. Therefore, copper is now considered as the best material for the next generation IC interconnection.
So far, copper deposition process is a relatively important process for IC or printed circuit board industries, especially for the fine circuit with high aspect ratio. Techniques employing copper as the interconnection in the integrated circuit generally deposit copper through one of following processes: sputtering, physical vapor deposition, chemical vapor deposition, electrochemical deposition and the like.
As to the physical vapor deposition, problems with respect to the overhangs of contact opening have been now in a very difficult state. As to the chemical vapor deposition, a difficulty to be solved is that non-volatile CuCl2 solid would be generated during the process. Therefore, substituting aluminum circuit with high conductive copper circuit must be conducted with other manners, such as copper deposition by electroplating, for example, that disclosed in U.S. Pat. No. 5,256,274. The depositing solution disclosed in that patent contained 12 ounce of copper sulfate pentahydrate per gallon water, 10% sulfuric acid, 50 ppm chloride ion and 0.4% additives. After researching and developing over 10 years, IBM Company claimed in the end of 1997 that a copper circuit of sub-0.25 micro on IC chip had been accomplished successfully by a electrochemical deposition method. Heretofore, the advantage of copper deposition has been recognized by the semiconductor industry.
Before deposition of copper layer by electroplating manner, a layer of diffusion barrier layer and a thin membrane of seed copper layer must be deposited on the silicon wafer by sputtering or chemical vapor deposition process. The diffusion barrier layer is, at the present time, composed predominantly of titanium nitride (TiN) or tantalum nitride (TaN) and is on a primary object of preventing the diffusion between the copper layer and the dielectric silicon dioxide (SiO2). The copper seed layer is used for conducting electric current during electroplating.
For the academic research on displacement reaction, Yosi Shacham-Diamand et al. proposed in The Electrochemical Society 144 P. 898-908, 1997, a formula for wet activating titanium nitride surface by a solution and yielding a Cu layer as the seed layer for electroplating or electroless plating, thereby preparation of the seed layer by the expensive PVD or CVD process can be eliminated. On the other hand, for the industrial research, IBM Company proposed a process for activating the surface titanium nitride with a solution containing hydrofluoric acid or copper sulfate and subsequently displacement depositing a copper seed layer. This process was described in detailed in their ROC Patent Application No. 86119270.
Deposition of a metal layer on the surface of the barrier layer material by displacement deposition had been taught in several U.S. patents. For example, Baum et al. disclosed in U.S. Pat. No.4,574,095, a process for depositing palladium on a silicon substrate by catalyzing reaction under light irradiation, and subsequently depositing copper by electroless plating thereto.
Wong disclosed in U.S. Pat. No.5,358,907 that, using displacement plating, metal from IB, IIB, IIIA, IVB, VB, VIB, VIIB or VIIIB groups can be deposited on silicon substrate or silicon-containing compound, wherein the formulation of the displacement solution contained hydrofluoric acid (HF).
Valery M. Dubin et al. disclosed in U.S. No. 5,891,513 the use of the displacement process on the integrated circuit, wherein, a solution consisting of 0.001-2 mol/l of copper ion, 0.001-5 mol/l of fluoride ion, and 0.01-10g/l of surfactant could be used to deposit a copper seed layer on a titanium nitride substrate, and then carried out an electroless plating to increase the thickness of the copper layer.
There is still a need in the art a low cost process for fabricating a reliable copper interconnection structure useful for submicron wiring in the integrated circuit chip.
Accordingly, the invention relates to a low cost process for fabricating copper interconnection structure useful for submicron circuit wiring in the integrated circuit chip, the process comprising displacement depositing a thin metal layer on trench or via subjected to lithographic process, and then depositing a conductor therein by an electroplating or electroless plating process with a solution containing additives to form a metal wiring structure of interconnections or external circuit.
The invention provides also a process for fabricating a interconnection structure on an integrated circuit, the process comprising steps of depositing an insulating dielectric layer on a silicon wafer substrate; defining and forming lines or via through lithographic process and then depositing a layer of barrier material thereon; dipping said substrate in an activating solution and performing displacement deposition to deposit a thin metal layer on the surface of said barrier layer; electrochemical depositing a conductor therein with a solution containing surfactant to form interconnection circuit; and, finally, forming metal interconnection structure by a planarizing or chemical mechanical polishing process (CMP).
Accordingly, one object of the invention is to lower the producing cost of integrated circuit by activating a substrate with a solution and performing displacement deposition to deposit a metal layer thereon as a conducting layer required for subsequent electroplating process, whereby the copper seed layer as the conducting layer by physical or chemical vapor deposition can be avoided and hence the expensive cost on vacuum equipment can be saved.
Another object of the invention is to fill a substantially uniform copper layer on submicron wiring, wherein the aspect ratio of the via is greater than 1, while the width of the via or wiring can be as small as less than 0.2 micron.